The SILM workshop will be held by Zoom. Join us in room D: https://sba-research.zoom.us/j/88485306423
Do not hesitate to join our dedicated channel on Slack (#workshop_silm)
Timezone CEST – Europe/Paris (UTC +02:00)
Welcome session — 08:50-09:00 CEST – Guillaume Hiet and Jan Tobias Muehlberg
| 08:50-09:00 | Workshop introduction |
Session 1 — 09:00-10:10 CEST
| 09:00-09:45 | Invited talk – Harmonizing Performance and Isolation in Microkernels with New Hardware by Zeyu Mi [slides] |
| 09:45-10:00 | FlushBlocker: Lightweight mitigating mechanism for CPU cache flush instruction based attacks by Shuhei Enomoto (Tokyo University of Agriculture and Technology) and Hiroki Kuzuno (Intelligent Systems Laboratory, SECOM Co, Ltd.) [article] |
| 10:00-10:10 | Q&A |
Break — 10:10-10:30 CEST
Session 2 — 10:30-12:05 CEST
| 10:30-11:15 | Invited talk – Better Foundations for Secure Software using Trusted Hardware and Verification by Shweta Shinde [slides] |
| 11:15-11:30 | Borrowed Capabilities: Flexibly Enforcing Revocation on a Capability Architecture by Thijs Vercammen (KU Leuven), Thomas Van Strydonck (KU Leuven), and Dominique Devriese (Vrije Universiteit Brussel) [article] [slides] |
| 11:30-11:45 | Damas: Control-Data Isolation at Runtime through Dynamic Binary Modification by Camille Le Bon (Univ Rennes, Inria, CNRS, IRISA), Erven Rohou (Univ Rennes, Inria, CNRS, IRISA), Frédéric Tronel, (CentraleSupelec, Inria, CNRS, IRISA), and Guillaume Hiet (CentraleSupelec, Inria, CNRS, IRISA) [article] |
| 11:45-12:05 | Q&A |
Lunch Break — 12:05-13:30 CEST
Session 3 — 13:30-15:15 CEST
| 13:30-14:15 | Invited talk – Plundering and Pillaging with Voltage: Software and Hardware-based Fault-injection Attacks against SGX by Flavio Garcia [slides] |
| 14:15-15:15 | Panel debate : Future directions for secure hardware/software interfaces |
Break — 15:15-15:30 CEST
Session 4 — 15:30-16:20 CEST
| 15:30-15:45 | Semi-automatic verification of ISA security guarantees in the form of universal contracts Sander Huyghebaert (Vrije Universiteit Brussel), Steven Keuchel (Vrije Universiteit Brussel), and Dominique Devriese (Vrije Universiteit Brussel) [article] [slides] |
| 15:45-16:00 | Virtual Platform to Analyze the Security of a System on Chip at Microarchitectural Level by Quentin Forcioli (LTCI, Télécom Paris, Institut Polytechnique de Paris), Jean-Luc Danger (LTCI, Télécom Paris, Institut Polytechnique de Paris), Clémentine Maurice (Univ. Lille, CNRS, Inria), Lilian Bossuet (Laboratoire Hubert Curien), Florent Bruguier (LIRMM, Univ. Montpellier, CNRS), Maria Mushtaq (LIRMM, Univ. Montpellier, CNRS), David Novo (LIRMM, Univ. Montpellier, CNRS), Loïc France (LIRMM, Univ. Montpellier, CNRS), Pascal Benoit (LIRMM, Univ. Montpellier, CNRS), Sylvain Guilley (Secure-IC), and Thomas Perianin (Secure-IC) [article] |
| 16:00-16:20 | Q&A |
Closing remarks — 16:20 CEST
Invited Talks
Zeyu Mi – Harmonizing Performance and Isolation in Microkernels with New Hardware Features
| Bio: Dr. Zeyu Mi is a research assistant professor at the School of Software at Shanghai Jiao Tong University (SJTU), China. He earned his Ph.D. degree in computer science from SJTU in 2020. His research interests include system virtualization, operating systems, and system security. Currently, he focuses on using new hardware features to build next-generation virtualized software. His papers have been published at top conferences, including USENIX Security, EuroSys, and USENIX ATC. | |
| Abstract: Microkernels have been extensively studied over decades. However, IPC (Inter-Process Communication) is still a major factor of run-time overhead, where fine-grained isolation usually leads to excessive IPCs. In this talk, we discuss applying new Intel hardware features to design two new IPC facilities for microkernels. First, we leverage Intel VMFUNC to design SkyBridge that allows a process to directly switch to the virtual address space of the target process with no involvement of the kernel. SkyBridge retains the traditional virtual address space isolation and thus can be easily integrated into existing microkernels. Second, we retrofit Intel Memory Protection Key for Userspace (PKU) to build UnderBridge, which moves the OS components of a microkernel between user space and kernel space at runtime to further optimize IPC performance while enforcing consistent isolation |
Flavio Garcia – Plundering and Pillaging with Voltage: Software and Hardware-based Fault-injection Attacks against SGX
| Bio: Flavio Garcia is a Professor of Computer Security and EPSRC Fellow in the Centre for Cyber Security and Privacy at University of Birmingham. His work focuses on the design and evaluation of cryptographic primitives and protocols for embedded and automotive systems. Garcia’s work has been published at top venues including Usenix Sec, IEEE S&P, ACM CCS and CHES, and have received Best Paper awards from IEEE Security & Privacy (Oakland) and Usenix Woot. | |
| Abstract: In this talk we present two voltage glitching attacks against Intel SGX. The first one (Plundervolt) provides a software-based attack where a privileged adversary abuses an undocumented Intel Core voltage scaling interface to corrupt the integrity of Intel SGX enclave computations. The second attack (VoltPillager) presents a low-cost hardware tool for injecting messages on the Serial Voltage Identification bus between the CPU and the voltage regulator on the motherboard. We leverage this powerful tool to mount fault-injection attacks that breach confidentiality and integrity of Intel SGX enclaves on fully patched systems. |
Shweta Shinde – Better Foundations for Secure Software using Trusted Hardware and Verification
| Bio: Shweta Shinde is an assistant professor at ETH Zurich, where she leads the Secure and Trustworthy Systems Group. Her research is broadly at the intersection of trusted computing, system security, program analysis, and formal verification. Her work has been published at top venues in security (IEEE S&P, ACM CCS, Usenix Security, NDSS), programming languages (PLDI), and software engineering (FSE). Her research has been commercialized at three start-ups and has led to a direct impact at various companies. Prior to joining ETH, she was a postdoctoral scholar at UC Berkeley. Shweta received her Ph.D. from the National University of Singapore in 2018 where she was awarded the Dean’s Graduate Research Excellence Award. | |
| Abstract: Software systems are ever-growing in size and complexity while being rife with vulnerabilities. Patches and defenses are continuously deployed, but the software attack surface is extremely large and attackers invariably find ways to gain a persistent foothold. An effective way to end the arms race between vulnerabilities and defense tools is by isolating the software using trusted hardware. With such isolation, what is the least amount of code that needs to be bug-free to securely run user applications? At the moment, even after using trusted hardware, this number can be upwards of a few million lines of code. Can we do any better? In this talk, I present foundational approaches to safeguard applications against large and potentially buggy software. I highlight principled ways of using hardware isolation and software verification to securely execute Linux applications while only trusting a few thousand lines of code. Overall, such designs point to a new way of executing secure applications. Finally, I will highlight the ongoing initiatives and research directions for building the next generation of better, trusted, and verified secure software. |
